Functional Verification Environment for Universal Serial Bus 3.0

• Main Authors: Jui Wang, 王睿
• Other Authors: 郭斯彥
• Format: Others
• Language: en_US
• Published: 2010
• Online Access: http://ndltd.ncl.edu.tw/handle/66200702898036751727

碩士 === 臺灣大學 === 電子工程學研究所 === 98 === The complexity of digital electronic circuit is growing dramatically these years, making verification process, which is considered the major bottleneck, more challenging. Moreover, the rapid renew of various technologies is forcing IC industry to shorten the time-to-market of a product, which means to compress the time period of designing, verification, and tape-out process. To address this problem, an effective and comprehensive verification environment is necessary. In this thesis, we design and implement a layered verification environment based on object oriented language, SystemVerilig. Utilizing the Constrained-Random Stimulus Generation property in SystemVerilig, the stimulus is generated randomly in a restricted subset, thus it not only raises the probability of hitting a bug but also makes programming task easier. The object oriented characteristic and built-in functional coverage mechanism makes this environment more efficient and reliable. Universal Serial Bus is a commonly used interconnect interface, so we use it as an example to design and implement a verification environment. Hoping to offer some effort to IC industry and giving out an implementation for related studies to compare the pros and cons, we present this work.