An Ultra-low Power Analog to Digital Converter

• Main Authors: Hung-Yen Tai, 戴宏彥
• Other Authors: 陳信樹
• Format: Others
• Language: en_US
• Published: 2010
• Online Access: http://ndltd.ncl.edu.tw/handle/94016340918028956067

碩士 === 臺灣大學 === 電子工程學研究所 === 98 === A 10-bit 800KS/s SAR ADC (Successive Approximation Register Analog to Digital Converter) is demonstrated in a standard TSMC 90nm process. This SAR ADC can operate well in low supply voltage. By using split-capacitor technique, its power consumption is only 2.88uW. The FoM (Power / 2ENOB / Fs) of this chip is 10.2fJ / conversion-step. Since the power of SAR ADC approximates to 0.5*C*V2*f, it can save power by reducing the MOS capacitor and lowering the supply voltage. This chip is implemented in advanced process and its supply voltage is 0.5V. In such a low voltage, it uses a charge pump to fully turn on or turn off the sampling switch. For the purpose of using NMOS input pair comparator, the level-shift method is adopted. The measurement results show that the SFDR is 66.19dB, the SNDR is 52.72dB, and the ENOB is 8.47-bit. The chip size occupies 0.49 mm2, and the active area is only 0.038 mm2.