An Ultra-low Power Analog to Digital Converter
碩士 === 臺灣大學 === 電子工程學研究所 === 98 === A 10-bit 800KS/s SAR ADC (Successive Approximation Register Analog to Digital Converter) is demonstrated in a standard TSMC 90nm process. This SAR ADC can operate well in low supply voltage. By using split-capacitor technique, its power consumption is only 2.88uW....
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/94016340918028956067 |