Task Scheduling for Efficient Memory Bandwidth Utilization on CMPs
碩士 === 臺灣大學 === 資訊工程學研究所 === 98 === Memory Wall is a well-known obstacle to processor performance improvement. The popularity of multi-core architecture will further exaggerate the problem since memory resource is shared by all the cores. Interferences among requests from different cores may prolong...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/56102928507045398258 |