| Summary: | 博士 === 國立清華大學 === 奈米工程與微系統研究所 === 98 === Due to the development of portable consumer products, minimization and multi-functions of an electronic device is the next challenge for the semiconductor industry. Sensing function and integration compatibility provided by micromachining technology is the promising technique to overcome those issues. Also, nowadays a heterogeneous integration microsystem could be achieved by System-in-Packaging (SiP) based on micromachining technology. This research focuses on the development of the microdevice which is suitable for heterogeneous integration. Through-Silicon Via (TSV) technology was applied to implement this goal in applications like three-dimensional packaging and integration of microdevice. The core technology is to embed TSV inside MEMS substrate wafer to fabricate MEMS device and packaging. This research will utilize the MEMS device with embedded TSV, either in wafer-level packaging (WLP) and multi-functions microsystem by stacking vertically. In the first part of this research, TSV fabricated by metal electroplating was achieved. And integration of this technique in SOI-MEMS wafer is demonstrated. Then anodic bonding was combined in process flow to achieve WLP of single-crystalline silicon device. In the second part of this research, a novel glass reflow technology was utilized to fabricate low-resistivity silicon TSV. SOG-MEMS device with embedded TSV was fabricated. Both of those devices are 3D stacking compatible and WLP can be achieved by wafer bonding technology. Third part of this research is glass microprobe array with embedded silicon vias by glass reflow technology. By TSV technique, 3D microprobe array, as a probing tool for biological and neural signals, can be accomplished by stacking of 2D microprobe array.
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