應用電荷汲引技術於高介電係數閘極電晶體階段缺陷增生與空間之量測研究

• Main Authors: Tsao, Che-Hao, 曹哲豪
• Other Authors: Chang-Liao, Kuei-Shu
• Format: Others
• Language: zh-TW
• Published: 2010
• Online Access: http://ndltd.ncl.edu.tw/handle/26957212769329201613

碩士 === 國立清華大學 === 工程與系統科學系 === 98 === For satisfy ITRS rule to keep device scale down. General method use high-kapa material which replaced silicon dioxide MOSFET to overcome gate leakage problem. But there are more issues in the process. Such as charge trapping, threshold voltage shift, mobility degradation, et al. Becasue of the problem mentioned, technique to detect interface traps and oxide traps be developed. In the first part of thesis, introduce charge pumping technique. Use CP method to measure interface trap and border trap in different gate dielectric thickness MOSFET. To understand the trap energy distribution in silicon bandgap. In the second part of thesis, experiment study the Constant-Voltage-Stress which shift threshold voltage in different time. The staged degredation can separate as trapping and stress-induced defects. After, experimental study discover oxide trap dominate the threshold voltage shift in trapping stage. And stress induced trap generation come from oxide trap are more serious. So, improve oxide trap in MOSFET would be first priority to satisfied life time restraint. In the last part of thesis, experiment combine depletion region method and frequency method in Charge Pumping technique to measure device's junction side spatial distribution. And use this 3D distribution to detect trap generation after CHCS and PBTI reliability test. Experimental study discover the stress could be different spatial damaged in device. Wish using this knowledge help to improve device.