Fast Locking Adaptive PLL using Dual-Edge Phase-Frequency Detector
碩士 === 國立清華大學 === 電機工程學系 === 98 === In the phase-locked loop (PLL) design, the locking time and the jitter depend on the loop bandwidth. Increasing the loop bandwidth of the PLL can reduce the locking time, but also increase the jitter. In order to gain the fast locking time and the low jitter,...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2010
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/14149815929839246357 |