| Summary: | 碩士 === 國立清華大學 === 電子工程研究所 === 98 === The goal of this thesis is using CMOS integrated circuit (IC) technology (TSMC 0.35 ?慆 CMOS process) to combine with MEMS technology for implementing a novel CMOS-MEMS neural recording probe with suitable die-level post-fabrication. We design a voltage sensing buffer and construct a sensing electrode array with minimized parasitic effect. In order to reduce the number of I/O pad, the 16-to-1 multiplexer has been realized such that the total amount of output pads can be minimized. The last stage is an operational amplifier, which is used to amplify the neural signals.
During the post-fabrication, we use the thin-film technique to grow a biocompatible metal layer on electrode sites for detecting the neural signals. A chromium mask is used for defining the probe shape and as an etch-protection layer when we remove the silicon substrate and silicon dioxide layer. Finally, the probe is released by using a deep reaction ion etch. The voltage buffer is a common-drain amplifier (source follower), and we design a passive tunable first-order high pass filter at input node to set the dc-bias for the amplifier and to reject low frequency noise. Furthermore, the switch is built based on the transmission gate in our multiplexer. The gain stage is two-stage frequency compensation operational amplifier, it has a high gain and a low noise characteristic.
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