Layout-Aware Multiple Scan Tree Synthesis for 3D IC
碩士 === 國立中山大學 === 資訊工程學系研究所 === 98 === In the process of continuous scaling improvement under a single system-on-chip which contains millions of logic gates, testability of the design becomes more and more important and thus multiple scan tree test architecture can effectively reduce test time and t...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/38435313695760725443 |