| Summary: | 碩士 === 國立東華大學 === 電子工程研究所 === 98 === With the rapid progress of semiconductor process in recent years, we have been able to put more than hundreds of millions transistors into a single chip. The circuit characteristics in a large-scale chip have therefore changed significantly, while the transistor count and clock frequency of the chip keep increasing. As the transistors size and working voltage are getting smaller and lower, the connection design between IP blocks within the chip has become increasingly complex. On such advanced chip, signal transmission is no longer as stable and reliable as before. Since the signal is more susceptible to wire delay, noise, soft error, and synchronization, these factors affects the occurrence of timing errors.
This thesis describes a timing-error-tolerant design of pipeline circuits. In such architecture, the pipeline stage buffer is replaced with a new design circuit to support timing error resilience. The organization of the circuit tolerates the timing errors with the ability to detect and correct such problems in the pipeline.
We have applied the technique to systolic arrays. Two systolic architectures for matrix multiplication are designed with our proposed techniques, including linear and hexagonal systolic arrays. We use hardware description language to design and simulate them, and verify the timing error tolerance of the circuits. Furthermore, the circuit synthesis and physical design tools are also employed to realize our design. The results show that in order to achieve timing error resilience, we need to pay a portion for circuit speed and chip area. However, with the data width increasing, such overhead decreases and can be hidden and negligible for designs with high data width.
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