A Sub-1V Phase-Locked Loop with Constant KVCO Technique
碩士 === 國立中央大學 === 電機工程研究所 === 98 === The issue of energy saving and carbon reduction is more and more important on circuit design. Phase-locked loop (PLL) is one of the important blocks in communication system. Thus, the power consumption of PLL is not able to ignore. To reduce supply voltage is the...
Main Authors: | , |
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Other Authors: | |
Format: | Others |
Language: | zh-TW |
Published: |
2009
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Online Access: | http://ndltd.ncl.edu.tw/handle/72196391495539704346 |