| Summary: | 碩士 === 國立中央大學 === 電機工程研究所 === 98 === Duo to the fast growth of leakage power dissipation,
power-gating technique is a often used to reduce leakage
power and dynamic power simultaneously. While designing a
power gating design, two critical issues are often
discussed: sleep transistor sizing and wakeup scheduling.
However, solving the two critical issues requires the same
essential information, the supply current waveform of the
main circuits. Most existing approaches assume that the
current information of the main circuits can be obtained
from transistor-level simulation. Although this approach can
obtain highly accurate current waveforms, it often requires
heavy simulation overhead. Until now, not too many
researches focus on studying a fast and efficient current
model for power gating designs to analyze the wake-up
current impacts. Therefore, a gate-level current model is
proposed using standard cell library format to estimate the
wake-up current. According to the input values of each cell,
the proposed method will choose an existing switching
current waveform and modify it to build the wake-up current
model. Thus, the wake-up current waveform can be obtained by
the proposed approach without extra characterization, except
the input values and the equivalent resistance and
capacitance of the power gate. The experimental results show
that the proposed gate-level wake-up current model can
provide accurate enough current waveform to help designer
analyze the rush current effects at early design stages.
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