Maximum Wake-up Current Estimation at Gate-level with Standard Library Information
碩士 === 國立中央大學 === 電機工程研究所 === 98 === Duo to the fast growth of leakage power dissipation, power-gating technique is a often used to reduce leakage power and dynamic power simultaneously. While designing a power gating design, two critical issues are often discussed: sleep transistor sizing and wakeu...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/66358161523506804586 |