| Summary: | 碩士 === 國立中央大學 === 電機工程研究所 === 98 === In recent years, due to rapid development of network and processor, transmit a lot of data quickly becomes the main motivation of transmission system. Therefore, conventional parallel bus is replaced gradually by high-speed serial link transmission system. But, when the system operates at gigahertz level frequency, the data of high frequency component pass through the channel will distort and degrade. For this reason, this thesis hopes to realize a 5-Gb/s inductorless analog equalizer to compensate channel loss, and can be applied in PCI Express Generation II system.
This thesis proposes an inductorless analog equalizer that compensates for the PCI Express Generation II channel loss of 14-dB at 2.5-GHz. This equalizing filter uses low voltage zero generator (LVZG) to generate high-frequency gain boosting without using inductors. The spectrum-balancing technique eliminates the needing for regulating comparator. The power detector (POD) combines current steering technique and pre-amplifier circuit to enhance the voltage swing, therefore relax the gain requirement of error amplifier. The test chip is implemented in TSMC 0.18-μm 1P6M CMOS technology. It works at power supply 1.6-V with 17.6-mW (excluding the output buffer). The total chip area is 0.54-mm2 with pads, the core area is 0.1-mm2 (including output buffer), and output peak-to-peak jitter is 0.28-UI.
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