Register Allocation of JIT Compiler for Mixed-Width ISA for Code Size Reduction
碩士 === 國立交通大學 === 資訊科學與工程研究所 === 98 === In embedded system, memory is a precious resource, and that reducing program code size becomes an important issue. One promising approach for code reduction is employing “mixed-width instruction set architecture (ISA)”. This kind of architecture usually provid...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2009
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| Online Access: | http://ndltd.ncl.edu.tw/handle/66225698394012346263 |