A Phase Locked Loop for MB-OFDM UWB Frequency Synthesizer Application
碩士 === 國立成功大學 === 電機工程學系碩博士班 === 98 === The frequency synthesizer is very important circuit of wireless communication system. To achieve different communication system standards, the frequency plan and specifications are also dissimilar. In this thesis a Phase Locked Loop (PLL) is designed for the M...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/90731832883485482570 |