A 10-bit 100MS/s Pipelined A/D Converter with PD-BII
碩士 === 國立成功大學 === 電機工程學系碩博士班 === 98 === A low power 10-bit 100-MHz pipelined ADC was implemented in a TSMC 0.18-μm 1P6M CMOS process in this thesis. Opamps with pseudo differential bias and input interchanging (PD-BII) architecture are used as alternatives to opamp-sharing scheme for low power consu...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/85125846142189149187 |