Junction Efficiency for <110> Nano-regime CESL Strained MOS Devices with Different Si Capping Layers and Temperatures

• Main Authors: Ren-Hau Yang, 楊人澔
• Other Authors: Mu-Chun Wang
• Format: Others
• Language: zh-TW
• Published: 2011
• Online Access: http://ndltd.ncl.edu.tw/handle/43766584516659056386

碩士 === 明新科技大學 === 電子工程研究所 === 99 === With the semiconductor production technology promotion, the MOSFET manufacturing technology was evolved from 100-um node to 45-nm node or beyond, following the Moore’s law to shrink the feature sizes of the transistor devices, especially in gate length and width. How to promote the device performance under device shrinkage is a huge task and one of the mainly improved objectives for each advanced process evolution. Generally, the strained channel, SiGe channel, of MOSFET was fabricated by the lattice length mismatch between Si and Ge atoms. The SiGe channel was usually performed with uni-axial and bi-axial strained technology. To fit the requirements of electron/hole mobility in strained n/pMOSFET, respectively, the uni-axial strained technology is essential which provides the respective strained directions, X-, Y- and Z-directions. Some literatures had pointed out that the electron mobility and the hole mobility were obviously promoted with the tensile strain in X-Y plane. For p-channel device, the increase of hole mobility is possibly attributed to the reduction of effective hole mass. For n-channel device, the carrier mobility is increased by the reduction in both inter-valley scattering and inter-band scattering. In this study, we will discuss the junction efficiency for <110> nano-regime CESL strained MOS devices with different Si capping layers and temperatures, and analyze the electrical characteristics of p-type devices. Some literatures mentioned that the n-type devices in the CESL compressive strain illustrated the weak performance. Therefore, it will be ignored in this study. In this work, the temperature stress on the devices varied from 25℃ to 125℃. The characteristic analysis among different Si-cap thicknesses (24Å and 39Å) and the non-strained will be executed. Furthermore, the edge or bulk junction leakage among them will be probed and correlate the related failure mechanisms.