Junction Efficiency for <110> Nano-regime CESL Strained MOS Devices with Different Si Capping Layers and Temperatures
碩士 === 明新科技大學 === 電子工程研究所 === 99 === With the semiconductor production technology promotion, the MOSFET manufacturing technology was evolved from 100-um node to 45-nm node or beyond, following the Moore’s law to shrink the feature sizes of the transistor devices, especially in gate length and width....
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| Format: | Others |
| Language: | zh-TW |
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2011
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| Online Access: | http://ndltd.ncl.edu.tw/handle/43766584516659056386 |