A Study of 45-nm-node Process n/p Strained Silicon Transistors with Silicon Capping Thicknesses

碩士 === 明新科技大學 === 電子工程研究所 === 98 === The MOSFET technology was evolved from 100-um node to 45-nm node due to the cost consideration and marketing competition. The device performances are also directly improved. In the recent stage, some researchers carried out that the strained silicon technology co...

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Bibliographic Details
Main Authors: Hsiu-Yen Yang, 楊修彥
Other Authors: Mu-Chun Wang
Format: Others
Language:zh-TW
Published: 2010
Online Access:http://ndltd.ncl.edu.tw/handle/67732794571209722827
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Summary:碩士 === 明新科技大學 === 電子工程研究所 === 98 === The MOSFET technology was evolved from 100-um node to 45-nm node due to the cost consideration and marketing competition. The device performances are also directly improved. In the recent stage, some researchers carried out that the strained silicon technology could effectively increase the MOSFET’s mobility. Generally, the strained channel, SiGe channel, of MOSFET was fabricated by the lattice length mismatch between Si and Ge atoms. The SiGe channel was usually performed with uni-axial and bi-axial strained technology. To fit the requirements of electron/hole mobility in strained n/pMOSFET, respectively, the uni-axial strained technology is essential which provides the respective strained directions, X-, Y- and Z-directions. Some literatures had pointed out that the electron mobility and the hole mobility were obviously promoted with the tensile strain in X-Y plane. For p-channel device, the increase of hole mobility is possibly attributed to the reduction of effective hole mass. For n-channel device, the carrier mobility is increased by the reduction in both inter-valley scattering and inter-band scattering. In this study, the strained devices were processed with thicknesses, 15 Å, 30 Å, of silicon capping layers. To understand the relationship of silicon capping effect impacting the strained device, the parameters and characteristics of tested devices, such as input/output characteristics, gate leakage current, breakdown voltage, punch through effect, subthreshold slope, drain-induced barrier lowering (DIBL), and threshold voltage roll-off, were extracted and correlated to the adjusted process parameter. Through this analysis effort, the optimal process recipe will be recommended.