Advanced Layout Technology Considering Reliability and Process Variation
碩士 === 輔仁大學 === 電子工程學系 === 98 === The device size has been developed from deep sub-micron to nanometer generation accompanying with the evolution of semi-conductor process technology in order to improve the performance of the integrated circuit, operation speed and the cost. However, there are probl...
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| Format: | Others |
| Language: | zh-TW |
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2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/10318104520226733186 |
| Summary: | 碩士 === 輔仁大學 === 電子工程學系 === 98 === The device size has been developed from deep sub-micron to nanometer generation accompanying with the evolution of semi-conductor process technology in order to improve the performance of the integrated circuit, operation speed and the cost. However, there are problems of reliability, process variation and yield lost according to the size reduction, which the circuit designer can not get by simulation. Therefore, the way to improve these invisible issues by physical layout will be an important lesson.
This thesis is focused on the process variation and reliability at advance technology so that we can reduce the yield lost and make mass production more smoothly by the skill of physical layout.
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