Two-point calibration processor chip design using a clock-gated method
碩士 === 中原大學 === 電子工程研究所 === 98 === Clock gating is a dynamic power reduction method in which the clock signals are stopped for selected register banks during times when the stored logic values are not changing , clock gating is a well-established power-saving technique that has been used for years...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/t5592g |
| Summary: | 碩士 === 中原大學 === 電子工程研究所 === 98 === Clock gating is a dynamic power reduction method in which the clock signals are stopped for selected register banks during times when the stored logic values are not changing , clock gating is a well-established power-saving technique that has been used for years .
We use low-power standard cell library and clock gating method to implementing a Two-Point Calibration (TPC) processor with Low Power Controller (LPC) for Ion-Sensitive Field-Effect Transistor (ISFET). Event-driven power analysis indicated a power saving of 87.89% during the low power mode of TPC chip. Availability of this clock-gated low-power standard cell library allows us to optimize the power consumptions of our portable ISFET systems, such as pH meters and remote sensor nodes for continuous water quality and environment monitoring applications. The TPC is based on TSMC 0.35um 2P4M 3.3V CMOS technology.
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