Two-point calibration processor chip design using a clock-gated method
碩士 === 中原大學 === 電子工程研究所 === 98 === Clock gating is a dynamic power reduction method in which the clock signals are stopped for selected register banks during times when the stored logic values are not changing , clock gating is a well-established power-saving technique that has been used for years...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/t5592g |