Algorithmic Noise-Tolerance Multiplier Design via Redundant Fixed-Width Multiplier
碩士 === 長庚大學 === 電機工程學系 === 98 === In this thesis, we proposed a new algorithmic noise tolerant (ANT) multiplier architecture by using fixed-width multiplier to build the replica redundancy block. In this way, the computation error can be corrected with lower power consumption and more area-efficient...
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| Format: | Others |
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2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/93309771135779182092 |