A Wide-Range All-Digital Delay-Locked Loop in 65nm CMOS technology

• Main Authors: Chia-Lin Chang, 張嘉麟
• Other Authors: Ching-Che Chung
• Format: Others
• Language: en_US
• Published: 2010
• Online Access: http://ndltd.ncl.edu.tw/handle/38692773515088237722

碩士 === 國立中正大學 === 資訊工程所 === 98 === A wide-range all-digital delay-locked loop is proposed in this thesis. Based on the binary search scheme, the locking time can be reduced. Besides, the proposed leakage delay unit (LDU) can easily generate a large delay to reduce the difficulties to build up the high-speed digital counter in the cycle-controlled delay unit (CCDU) for a very low frequency operation. By using the cycle-controlled delay unit (CCDU), it reuses the delay units to enlarge the operating frequency range rather than cascading a large amount of delay units. Thus, the chip area can be reduced, too. A 600 kHz to 1.3 GHz all-digital delay-locked loop has been fabricated in UMC 65nm CMOS technology. The proposed DLL consumes a maximum power of 2.6 mW at 1.2 GHz. When the operating frequency is 1.2 GHz, the measured rms jitter and peak-to-peak jitter is 3.38 ps and 39.29 ps, respectively.