A Wide-Range All-Digital Delay-Locked Loop in 65nm CMOS technology
碩士 === 國立中正大學 === 資訊工程所 === 98 === A wide-range all-digital delay-locked loop is proposed in this thesis. Based on the binary search scheme, the locking time can be reduced. Besides, the proposed leakage delay unit (LDU) can easily generate a large delay to reduce the difficulties to build up the hi...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/38692773515088237722 |