A Clock Routing Algorithm for Structured ASIC with Predefined Metal Layers
碩士 === 元智大學 === 資訊工程學系 === 97 === Structured ASIC design methodology is invented to fill the gap between standard cell design and FPGA. Previous researches about standard cell like structured ASIC design do not focus on clock skew issue. In this thesis, we propose a clock routing algorithm for struc...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2009
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| Online Access: | http://ndltd.ncl.edu.tw/handle/95150012539934776107 |