The Design of All-Digital Cyclic Clock De-skew Buffer

• Main Authors: Wei-Young Jeng, 鄭惟陽
• Other Authors: Chrong-sii Hwang
• Format: Others
• Language: zh-TW
• Published: 2009
• Online Access: http://ndltd.ncl.edu.tw/handle/89492893972447883390

碩士 === 雲林科技大學 === 電機工程系碩士班 === 97 === This thesis presents an all-digital Cyclic Delay-Locked Loop. Generally Delay-Locked Loop can be divided into two kinds of digital and analog. For Digital model, the advantages are: high speed in operation, larger delay range and much better noise suppression. For Analog model, the advantages are: high resolution for delay time, low-jitter and small power consumption, the disadvantages are: larger locking time and easily sensitive to the process, voltage, and temperature variations. Generally Digital Delay-Locked Loop’s operation range is limited by the delay time of delay line and delay cell. The proposed architecture used one delay cell, counter and cyclic method. It can achieve large delay range for operation in lower frequency.