The Design of All-Digital Cyclic Clock De-skew Buffer
碩士 === 雲林科技大學 === 電機工程系碩士班 === 97 === This thesis presents an all-digital Cyclic Delay-Locked Loop. Generally Delay-Locked Loop can be divided into two kinds of digital and analog. For Digital model, the advantages are: high speed in operation, larger delay range and much better noise suppression. F...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2009
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| Online Access: | http://ndltd.ncl.edu.tw/handle/89492893972447883390 |