10-BIT 40-MS/S PIPELINE ANALOG TO DIGITAL CONVERTER
碩士 === 大同大學 === 電機工程學系(所) === 97 === In this thesis, we design a 10-bit 40MSample/s pipelined analog-to-digital converter (ADC) by TSMC 0.18μm 1P6M mixed signal process technology. The supply voltage is 1.8V. The ADC architecture is nine stage pipelined ADC in this design, we adopt 1.5-bit/per stage...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/46937665823288754411 |