| Summary: | 碩士 === 國立臺北科技大學 === 機電整合研究所 === 97 === In the study, we use 0.35μm CMOS-MEMS to design cantilever probe card, with through-silicon interconnections for IC testing. CMOS process provides multi-layer interconnections, which could assist the connection between the probe head the external devices, and reduce the difficulty of wiring layout. In addition, passive components or circuits could be integrated with the CMOS chip to improve the frequency bandwidth and measuring quality.
Still, many defects have existed in the MEMS fabrication of the probe card, which involves low contact force, short overdrive, complex process steps, and poor reliability and etc. Thus, the poor measurements would result from the problem that each single probe can not break through the oxidation on metal electrodes. The study successfully shows the fabrication of TSV model with the volume of 70 x 70 x 150 (μm3). The model was electroformed with copper as interconnections. Furthermore, LIGA-like process and electroless plating were adopted to deposit Nickel on probes to increase the strength of probes. The shape of probes was designed as S-like structure, which consisted of four layers of Aluminums. Also, the size of probes was with the width of 20μm and the length of 240μm. By using electroless plating, the thickness of probes increased within 28μm, and the probes were followed by polishing process to achieve the surface coplanarity. At last, the probes were released by ICP to complete the micro probes. Also the maximum contact force was measured at 83mN.
|
|---|
