Development of a 0.18μm , 60V ,Power Device based on SOI LDMOS Technology

• Main Authors: Yu Shan Hsu, 許瑜珊
• Other Authors: Shao Ming Yang
• Format: Others
• Language: zh-TW
• Published: 2009
• Online Access: http://ndltd.ncl.edu.tw/handle/93344457966985952595

碩士 === 亞洲大學 === 資訊工程學系碩士班 === 97 === The high junction leakages, circuit latched issues, and high parasite capacitances happened in the device manufactured by junction isolation technology can be eliminated or improved if the device is manufactured by the thin SOI (Silicon-On-Insulator) technology. A CMOS compatible SOI technology with best tradeoff of performance and cost will be one of technologies used in the future roadmap of LDMOS devices. A CMOS compatible thin SOI LDMOS (Lateral Double-diffused MOSFET) device, with 0.18 micron gate length, 0.02 micron gate oxide and 5 micron N-drift region, is proposed to achieve the optimal (BVoff) off-state breakdown voltage and on-state resistance (Ron) values. The characteristics of the proposed LDMOS device are verified by the two-dimensional process simulator TSuprem-IV and the device simulator Medici. The simulated results have shown that a device performance at the range of BVoff, 80 v, and Ron, 100 mohm-mm2, is attended. The on-state breakdown voltage is measured at 70V with an excellent safe operating area (SOA) performance for the drain source current versus on-state breakdown voltage. An analytical solution is also used to verify the electrical field and potential distribution obtained by the numerical simulations.