| Summary: | 碩士 === 南台科技大學 === 電子工程系 === 97 === Now days, the main development direction of ICs is to low-power consumption. In this way, the standby time will last longer.
In array multipliers, many products are generated by AND gates, the improvement in [1] is to replace AND gates with NAND gates and to replace adders with transmission gates. However, this approach suffers from poor fan-out. Hence, in this thesis, we try to use partial products and its inverted signals as the control signals of the full adders. The ‘Sum’ output can be generated by the 2-input XOR gates while the ‘Cout’ can be generated by the CMOS Logics. This will reduce computation complexity and reduce power consumption.
In this way, we synthesis 4x4 multiplier as well as 8x8 multiplier by using the mentioned methods. A Chip is also realized by TSMC 0.18 μm 1P6M CMOS process.
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