Implementation of low power array multiplier based on CMOS and PTL
碩士 === 南台科技大學 === 電子工程系 === 97 === Now days, the main development direction of ICs is to low-power consumption. In this way, the standby time will last longer. In array multipliers, many products are generated by AND gates, the improvement in [1] is to replace AND gates with NAND gates and to repla...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2009
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| Online Access: | http://ndltd.ncl.edu.tw/handle/21918717424649532697 |