A 5.3-GHz Frequency Synthesizer with a Novel Frequency Divider and Loop Filter
碩士 === 國立臺灣科技大學 === 電機工程系 === 97 === This thesis presents a 5.2GHz ~ 5.4GHz 4th order PLL frequency synthesizer in TSMC 0.18μm CMOS process. The number of channels is 16 and the channel spacing is 8MHz. A novel loop filter structure is employed such that the design procedure is simplified. A hardwar...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2009
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| Online Access: | http://ndltd.ncl.edu.tw/handle/74863855956348270054 |