Sample Plan Optimization for Overlay Control in Semiconductor Manufacturing

• Main Authors: Yi-Lun Yeh, 葉壹倫
• Other Authors: 蔡坤諭
• Format: Others
• Language: en_US
• Published: 2009
• Online Access: http://ndltd.ncl.edu.tw/handle/85406515352226555470

碩士 === 國立臺灣大學 === 電機工程學研究所 === 97 === A modern semiconductor device exists in three dimensions: throughout the course of its manufacturing, a chip experiences the patterning of approximately two dozen different layers, each of which must be precisely positioned with respect to the one beneath. In order to ensure the correct operation of the final device, this positioning (or alignment) is necessary to avoid the following problems like contact shorting to gate, and contact impinging on isolation. That will affect directly IC yield and performances. Over the years that lithography has been evolving, overlay alignment requirements have generally scaled linearity with the minimum feature size. For matching current overlay requirement, high order overlay model and field-to-field alignment have been applied to overcome this challenge. For applying these strategies more overlay measurement needs to be considered. However different overlay sample plans could led different results. The MOPE - maximum overlay predicted error could be used for judge current sample plan is suitable or not. First we analyse each component of overlay error to decide which model of order will match our economical requirement in both time consumption and overlay residual. Then we will proceed to analyse the MOPE based on single overlay data of each referred target which is partially chosen from original overlay data. This procedure will help us to find suitable samples for overlay parameter evaluation. Eventually, we will simulate our proposed control method using the Matlab software for the demonstration.