Sample Plan Optimization for Overlay Control in Semiconductor Manufacturing
碩士 === 國立臺灣大學 === 電機工程學研究所 === 97 === A modern semiconductor device exists in three dimensions: throughout the course of its manufacturing, a chip experiences the patterning of approximately two dozen different layers, each of which must be precisely positioned with respect to the one beneath. In or...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2009
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| Online Access: | http://ndltd.ncl.edu.tw/handle/85406515352226555470 |