A Quadratic Error Compensation in High-Speed 8-bit Current-Steering Digital to Analog Converter
碩士 === 國立臺灣大學 === 電機工程學研究所 === 97 === This thesis proposes an 8-bit 1GHz digital-to-analog converter with a segmented current steering architecture that consists of two parts, the upper 5-bit thermometer code and the lower 3-bit binary-weighted code. The design not only keeps the advantages of curre...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2009
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/51457244135558858347 |