0.5V MTCMOS Technique TSPC Dynamic Logic Circuit using for a Multiplier Design
碩士 === 國立臺灣大學 === 電子工程學研究所 === 97 === This thesis reports BP-DTMOS/MTCMOS technology used in the full adder and the multiplier for optimization of power consumption and speed performance. First， evolution trends of CMOS technique and the low voltage operation requirement of VLSI circuit are describe...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2009
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| Online Access: | http://ndltd.ncl.edu.tw/handle/24800048978462663543 |
| Summary: | 碩士 === 國立臺灣大學 === 電子工程學研究所 === 97 === This thesis reports BP-DTMOS/MTCMOS technology used in the full adder and the multiplier for optimization of power consumption and speed performance. First， evolution trends of CMOS technique and the low voltage operation requirement of VLSI circuit are described. Then BP-DTMOS technology is introduced. Chapter 2 describes the principle of low voltage dynamic logic circuit with and without latch using BP-DTMOS/MTCMOS technology. In addition， a full adder circuit using BP-DTMOS/MTCMOS technology is described. In Chapter 3， a dynamic logic circuit and DTMOS/MTCMOS technology pipelined multiplier using the 0.5V true single-phase clock (TSPC) is described. Chapter 4 is the conclusion and future work
of this research.
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