SiGe Quantum-Well/Quantum-Dot Devices and Saddle FinFETs

• Main Authors: Ping-Sheng Kuo, 郭平昇
• Other Authors: 劉致為
• Format: Others
• Language: en_US
• Published: 2009
• Online Access: http://ndltd.ncl.edu.tw/handle/30023899608742608322

博士 === 國立臺灣大學 === 電子工程學研究所 === 97 === In this dissertation, the SiGe metal-insulator-semiconductor devices are studied and we divide into the experiment part and the simulation part. First, the blockage of hole transport due to excess holes in SiGe dots was observed in the metal-oxide-semiconductor tunneling diodes for the first time. The 5 layers of self-assembled SiGe dots are separated by 74 nm Si spacers and capped with a 130nm Si. The incorporation of SiGe dots confines the excess holes in the valence band, and forms a repulsive barrier to reduce the hole transport current at positive and negative gate biases. A metal/oxide/n-Ge structure has been utilized as a photodetector. We use Al and Pt as the gate electrodes to evaluate the transport mechanism of the MOS detector. At negative gate bias, the dark current of the Al gate detector is composed of the thermal generation of minority carriers in the depletion region and the electron current tunneling from Al to conduction band of the n-type Ge substrate. However, for the Pt gate detector at negative gate bias, the electron tunneling from Pt to conduction band of the n-type Ge is greatly reduced due to the large work function of Pt (5.65 eV) as compared to Al (3.15 eV). The hole confinement due to the valence band offset of the Si/SiGe/Si quantum well causes the shrinkage of depletion region for the n-type Si/SiGe/Si Schottky barrier diodes with Pt gates. The shrinkage of depletion region at reverse bias increases capacitance and current. The conventional capacitor-voltage method can not be used to measure the barrier height of Si/SiGe/Si quantum well Schottky diodes due to the shrinkage of depletion region. The second part is the simulation work of saddle FinFETs for DRAM applications and Si/Ge/Si QW pFETs. No punch-through anti-doping is required for the Si/Ge/Si pFETs due to the shrinkage of depletion region. The saddle FinFETs are demonstrated to be more suitable than the bulk FinFETs for sub-50nm DRAM applications. We proposed new structure and optimized the doping profiles in source/drain to reduce the leakage current and word-line capacitance.