An Efficient FPGA Implementation of IEEE 802.16e LDPC Encoder

碩士 === 國立臺灣大學 === 資訊工程學研究所 === 97 === In this paper, a FPGA implementation of IEEE 802.16e LDPC encoder is presented. We employ parity bit prediction and correction to break up the data dependency within the encoding process. This encoder implementation can handle sixteen combinations of code rates...

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Bibliographic Details
Main Authors:	Chao-Yuan Yu, 游超元
Other Authors:	Mong-Kai Ku
Format:	Others
Language:	en_US
Published:	2009
Online Access:	http://ndltd.ncl.edu.tw/handle/81201518294166642685

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spelling	ndltd-TW-097NTU053920412016-05-04T04:31:31Z http://ndltd.ncl.edu.tw/handle/81201518294166642685 An Efficient FPGA Implementation of IEEE 802.16e LDPC Encoder 高效率IEEE802.16e編碼器設計與實作 Chao-Yuan Yu 游超元碩士國立臺灣大學資訊工程學研究所 97 In this paper, a FPGA implementation of IEEE 802.16e LDPC encoder is presented. We employ parity bit prediction and correction to break up the data dependency within the encoding process. This encoder implementation can handle sixteen combinations of code rates and code lengths defined in IEEE 802.16e standards. Efficient hardware architecture reduces the complexity and area of encoder that can handle rate: 1/2, 2/3, 3/4, 5/6 and code length: 576 to 2304. Results show that the proposed architecture outperforms conventional works in terms of throughput and throughput/area ratio. Mong-Kai Ku 顧孟愷 2009 學位論文 ; thesis 45 en_US
collection	NDLTD
language	en_US
format	Others
sources	NDLTD
description	碩士 === 國立臺灣大學 === 資訊工程學研究所 === 97 === In this paper, a FPGA implementation of IEEE 802.16e LDPC encoder is presented. We employ parity bit prediction and correction to break up the data dependency within the encoding process. This encoder implementation can handle sixteen combinations of code rates and code lengths defined in IEEE 802.16e standards. Efficient hardware architecture reduces the complexity and area of encoder that can handle rate: 1/2, 2/3, 3/4, 5/6 and code length: 576 to 2304. Results show that the proposed architecture outperforms conventional works in terms of throughput and throughput/area ratio.
author2	Mong-Kai Ku
author_facet	Mong-Kai Ku Chao-Yuan Yu 游超元
author	Chao-Yuan Yu 游超元
spellingShingle	Chao-Yuan Yu 游超元 An Efficient FPGA Implementation of IEEE 802.16e LDPC Encoder
author_sort	Chao-Yuan Yu
title	An Efficient FPGA Implementation of IEEE 802.16e LDPC Encoder
title_short	An Efficient FPGA Implementation of IEEE 802.16e LDPC Encoder
title_full	An Efficient FPGA Implementation of IEEE 802.16e LDPC Encoder
title_fullStr	An Efficient FPGA Implementation of IEEE 802.16e LDPC Encoder
title_full_unstemmed	An Efficient FPGA Implementation of IEEE 802.16e LDPC Encoder
title_sort	efficient fpga implementation of ieee 802.16e ldpc encoder
publishDate	2009
url	http://ndltd.ncl.edu.tw/handle/81201518294166642685
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An Efficient FPGA Implementation of IEEE 802.16e LDPC Encoder

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