An Efficient FPGA Implementation of IEEE 802.16e LDPC Encoder
碩士 === 國立臺灣大學 === 資訊工程學研究所 === 97 === In this paper, a FPGA implementation of IEEE 802.16e LDPC encoder is presented. We employ parity bit prediction and correction to break up the data dependency within the encoding process. This encoder implementation can handle sixteen combinations of code rates...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2009
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| Online Access: | http://ndltd.ncl.edu.tw/handle/81201518294166642685 |