Effects of the scaled charge trapping layer on SONOS type non-volatile memory
碩士 === 國立清華大學 === 電子工程研究所 === 97 === Recently, Flash technology is gradually migrated from floating-gate cells to charge-trapping devices due to lower operating voltage and two bits storage. However, it is also a great challenge to scale the conventional charge-trapping Flash cells for the need of h...
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| Format: | Others |
| Language: | zh-TW |
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2009
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| Online Access: | http://ndltd.ncl.edu.tw/handle/93668147445726615028 |
| Summary: | 碩士 === 國立清華大學 === 電子工程研究所 === 97 === Recently, Flash technology is gradually migrated from floating-gate cells to charge-trapping devices due to lower operating voltage and two bits storage. However, it is also a great challenge to scale the conventional charge-trapping Flash cells for the need of high voltage operations in channel-hot-electron (CHE) programming and band-to-band-hot-hole (BBHH) erasing.
This thesis experimentally examines the scaling effects of the nitride charge-trapping layers on Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) type Flash memory. The reduction of nitride charge trapping layer offers the enhancement of programming and erasing speed for the SONOS type memory cell. However, it leads to the serious degradations in the memory window during 10K programming/erasing cycling and the retention charge loss after 10K cycling stress. Trade-offs between the performance enhancement and cell reliability exist to limit the further scaling of charge trapping layers for future non-volatile memory cells.
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