考慮資源限制下有效率喚醒排程技術於感測器為基礎之電源閘控設計
碩士 === 國立清華大學 === 資訊工程學系 === 97 === Power gating has been a very effective way to reduce leakage power. One important design issue for a power gating design is to limit the surge current during the wakeup process. Normally, a wakeup scheduling is required to control turn-on times of sleep transistor...
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| Format: | Others |
| Language: | en_US |
| Online Access: | http://ndltd.ncl.edu.tw/handle/25777350413096620486 |