| Summary: | 碩士 === 國立清華大學 === 資訊工程學系 === 97 === As technology process getting smaller and smaller, many companies make effort in signal integrity of SoC (System-on-chip) and SiP (System-in-Package) interconnects in order to improve the yield. Both SoC and SiP are critical now, compare SoC with SiP, SiP includes wire bond and PCB, it has many advantages, such as lower cost, short time-to-market, efficient, and low-risk, while on-chip has better performance. But they both have a trend that they are getting smaller and smaller with higher frequency. Thus, there are some problems should be solved by designers, like parasitic effect and transmission line effect. Parasitic effects are common issues of signal integrity. When frequency increases and the interconnect size decreases, we should make the interconnect model from lumped to distributed to take the transmission line effect into account.
Parasitic capacitance is one of the parasitic parameters (RLCKG). It plays an important role both on low and high frequency and it makes interconnect consume more time to transmit the signal. This results in an unexpected performance of the designs. Capacitance extraction often needs to consider the ambient environment, while resistance extraction often considers only the target interconnect and inductance extraction considers the return path. If we can’t extract the capacitance accurately, we will get lower yield. Nowadays, the commercial tools for on-chip interconnect capacitance extraction are so mature and they assume their models to be lumped models. Also, the 3D capacitance extraction is needed, but it is inconvenient for us to describe an overall PCB structure and it takes a lot of time to extract the capacitance for the overall structure.
Due to the above reasons, in this thesis, we propose a method to use the 3D field solver (Raphael) to build capacitance tables for common interconnect of printed circuit board and write a look up table program to get the distributed capacitance from tables. Each critical net may need different tables. So, according to the trace case and parameters user entered, the look up program will find the corresponding table and do interpolation to get capacitance. This efficient way will help designers to quickly get distributed capacitance, not a lumped one.
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