Comparator-Based Cyclic Analog-to-Digital Conversion with Error-Trimming

• Main Authors: Li-Shen Chang, 張力申
• Other Authors: Robert Rieger
• Format: Others
• Language: en_US
• Published: 2009
• Online Access: http://ndltd.ncl.edu.tw/handle/m9t434

碩士 === 國立中山大學 === 電機工程學系研究所 === 97 === This thesis focuses on the analysis theory, circuit design, simulations, and chip measurements of the transfer stage in the continuously error-trimming comparator-based switched-capacitor charge transfer stage in the cyclic redundant-sign-digit (RSD) algorithm. Capacitor mismatching remains an insurmountable factor for switched-capacitor circuit designers. To correct errors which result from the capacitor mismatching, a continuous error-trimming circuit is generalized from a typical CBSC circuit. The analysis theory of the error-trimming operation describes the effects of the error-trimming circuit in the CBSC circuit, as well as the guidelines for trimming. The error-trimming operation is able to tune the gain and virtual condition of the charge transfer stage for canceling the gain and offset errors. The circuit is designed, with the 0.35μm 2-poly 4-metal TSMC process, in fully integral circuits. The circuit is simulated by a matlab simulator and an online Cadence Spectre simulator, to confirm how the operation works. Finally, chip measurements are recorded for verification and simulation comparisons.