Comparator-Based Cyclic Analog-to-Digital Conversion with Error-Trimming
碩士 === 國立中山大學 === 電機工程學系研究所 === 97 === This thesis focuses on the analysis theory, circuit design, simulations, and chip measurements of the transfer stage in the continuously error-trimming comparator-based switched-capacitor charge transfer stage in the cyclic redundant-sign-digit (RSD) algorithm....
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| Format: | Others |
| Language: | en_US |
| Published: |
2009
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| Online Access: | http://ndltd.ncl.edu.tw/handle/m9t434 |