Design of Various VLSI Sorting Accelerator Architectures
碩士 === 國立中山大學 === 資訊工程學系研究所 === 97 === In this thesis, various designs of VLSI sorter architectures are proposed. This thesis first presents a baseline serial sorter architecture built on a central memory module equipped with a single compare-and-swap (C&S) functional unit. A dedicated low-cost...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2009
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| Online Access: | http://ndltd.ncl.edu.tw/handle/30104592484973140713 |