VLSI Design of a Lower-Error andROM-Free Logarithmic Converter UsingTwo Symmetric Regions
碩士 === 國立屏東商業技術學院 === 資訊工程系(原資訊科技系) === 97 === In this thesis a lower-error and ROM-free logarithmic converter is proposed. The proposed converter can lead to area-efficient hardware implementation as it avoids the need of a ROM by employing simple computation units for logarithmic approximation. Ou...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2009
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/02462357130630623540 |