| Summary: | 碩士 === 國立高雄第一科技大學 === 電腦與通訊工程所 === 97 === This thesis presents a digital-controlled delay line with digital to voltage converter (DVC) to achieve fast locking. In addition, the digital to voltage converter is applied in a digitally controlled Delay Locked Loop (DLL). The advantages of combining digitally controlled and voltage-controlled delay line characteristics are (1) high-resolution of delay line (2) low jitter (3) low process variation. In conventional design, DLL is usually controlled by a voltage-controlled delay line with the charge pump. The shortcoming of this approach is slow locking time. Therefore, an all-digital controlled delay-locked loop was proposed. However, the jitter is large for all-digital delay locked loop. This thesis proposes a digital to voltage converter to achieve fast locking and low jitter delay locked loop.
In addition, this thesis presents a modified calibration technique in order to improve the phase offset caused by process, voltage, temperature. We improve the traditionally continuous calibration algorithm by divide and conquer. The proposed calibration algorithm simplifies the circuit effort and making it easy to implement.
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